Generating Reduced Finite State Machine from Concurrent Scenarios Using Static Partial Order Method

Finite state machine (FSM) representation is widely used to perform behavioural analysis and generate test cases from a set of hierarchically organized scenarios written in Message Sequence Charts (MSCs). Brute-force approach of translating MSCs into FSM is impractical, especially when scenarios are executed concurrently. In this paper, we describe how to identify a sequence of message exchanges that are semantically equivalent and apply partial order method to reduce the number of transitions in the FSM. We demonstrate that the proposed technique is scalable by describing the results of a case study in which reduced FSM was automatically generated from a partial specification of digital TV software. ACM Classification: D.2.4 (Software Engineering – Software/Program Verification)